1. Field of the Invention
This invention relates in general to the field of instruction execution in computers, and more particularly to an apparatus and method for generating an absolute address of a floating point register during decode of a floating point instruction.
2. Description of the Related Art
Historically, floating point hardware and integer hardware have been set apart within microprocessor architecture. Early microprocessors exhibited this segregation in the extreme: their floating point hardware and integer hardware were on entirely different integrated circuits. Floating point instructions were provided to an integer microprocessor for instruction decode, which then provided decoded micro instructions to a floating point coprocessor. The floating point coprocessor performed the specified floating point operations and supplied its results back to the integer microprocessor.
Although advances in integrated circuit technology have allowed for incorporation of floating point hardware into the same physical device as the remainder of the microprocessor, this legacy of integer/floating point hardware segregation has been retained so that older software programs would be able to execute on a newer microprocessor.
In an x86-compatible microprocessor, floating point instructions execute on operands stored in a floating point register file. The register file is viewed as a stack structure. A mechanism in the floating point unit keeps track of a register known as the top-of-stack. All x86 floating point instructions specify their register operands relative to the top-of-stack register. For example, an addition instruction, FADD ST(1), implicitly specifies the location of a first operand as being at the top-of-stack register, ST(0), and a second operand as being at a second register, ST(1), displaced by one address from the top-of-stack.
While relative specification of floating point registers is useful from a programming aspect, real world register files require absolute register addresses in order to access specified locations. As a result, conventional microprocessors have an initial stage in their floating point unit that is dedicated to converting relative references to floating point registers into absolute register addresses. More specifically, macro instructions are provided to the microprocessor with relative operand addresses. These instructions are decoded into micro instruction sequences, also with relative operand addresses. The floating point unit receives these floating point micro instructions and converts the relative operand addresses into physical addresses prior to execution of the instructions. In terms of a microprocessor clock, this conversion requires from one to three additional cycles for each micro instruction that enters the floating point unit. These additional cycles in the floating point pipeline cause delay to the overall time required to execute a software program. For a program having many floating point instructions, the associated delay is even more pronounced.
Therefore, what is needed is an apparatus and method that generates absolute references for floating point registers during translation of floating point macro instructions into associated micro instructions. In addition, what is needed is an apparatus and method that eliminates the need to convert relative register references to absolute references in a floating point unit.